1. Field of the Invention
The present invention relates to memory circuits, and in particular to a memory circuit equipped with an error correcting code system.
2. Description of the Related Art
With the continuous growth of their computing power and the rise of their operation frequency, the sensitivity of information processing systems to errors likely to corrupt data considerably increases. This is all the more sensitive since miniaturization of electronic components reduces the size of the electronic components contained in Very Large Systems Integration (V.L.S.I.) circuits and in particular the size of Read Access Memory (R.A.M) circuits integrated therein.
Thus, it can be noted that static storages whose load capacities are increasingly lower with the development of technologies, become particularly sensitive to electromagnetic fields and disturbances, which obviously is an important source of errors disturbing correct operation of electronic circuits.
Memory systems are conventionally protected against fugitive or random errors by being equipped with error correcting systems based on error correcting codes or ECC. As is known, redundant information—in the form of an ECC code —is introduced so that information integrity can be checked by computation upon fetching or even that one or more erroneous bits can be restored.
FIG. 1 illustrates a conventional architecture of a memory circuit equipped with such an error correcting system. Via an input bus 2 (for example, a 32-bit bus) data is sent to a static RAM 1, and to an encoder 4 that computes an error correcting code and then data and the error correcting code are stored in memory 1. Upon a read operation, a decoder again computes the error correcting code so that a comparator 6 compares the expected code with the code actually stored in memory. Any difference is then interpreted as an error and, according to the code used, one or more errors can be detected or corrected.
In general, the use of an error correcting code in a memory circuit is satisfactory and in particular in sensitive systems, such as telecommunication servers and routers. However, it is noted that the use of such a system usually penalizes the system's operating speed. Indeed, if one considers for example a circuit having an operation frequency of 200 MHz, this leaves 5 nanoseconds—i.e. very little time—to insert the computing time required by encoder 4.
Thus memory circuits functioning at high speed are not adapted to use an error correcting code, which is very regrettable since nowadays many applications are used for which operating speed goes hand in hand with data integrity and security.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.